Single bit half adder with carry and enable using VHDL

 

Single bit half adder with carry and enable using VHDL

 

Specifications:

• Inputs and outputs are each one bit
• When enable is high, result gets x plus y
• When enable is high, carry gets any carry of x plus y
• Outputs are zero when enable input is low

Step1:

Input and output ports are declared

Step 4: Structural Specification

 

Single bit half adder with carry and enable using VHDL